1. Field of the Invention
The present invention relates to a vertical bipolar junction transistor (BJT), and more particularly to a process for fabricating a vertical bipolar junction transistor that has a higher switching speed than that of conventional vertical bipolar transisitors.
2. Description of the Related Art
Vertical BJTs are well known in the integrated-circuit art. FIG. 1 (Prior Art) is a schematic cross section of a conventional vertical BJT. The vertical BJT is fabricated in an N-type silicon substrate 1, and includes a large P.sup.- -type base region 12 formed in the silicon substrate 1, an N.sup.+ -type emitter region 10 formed in the base region 12, a P.sup.+ -type contact region 14 for the base region 12, and an N.sup.+ -type collector region 16 formed in the silicon substrate 1.
The size of the emitter region 10 of the conventional vertical BJT is relatively large, producing to large junction capacitance which lowers the switching speed. The distance from the emitter region 10 to the collector region 16 is relatively long, producing a large collector resistance which also lowers the switching speed.